1. Field of the Invention
The invention relates to memory cell arrangements, processes for operating such arrangements and methods of fabricating such arrangements. Somewhat more particularly, the invention relates to a memory cell arrangement comprised of a semiconductor body of a first conductivity type in which a plurality of MNOS components, including source and drain zones of a second conductivity type, which is opposite to that of the first conductivity type, are arranged and includes a multi-layer gate insulating layer which covers the surface of the semiconductor body in the region between the source and the drain zones.
2. Prior Art
The operation mode of a MNOS (metal-nitride-oxide semiconductor) memory cell is based on the fact that in a MNOS field effect transistor, the conductance state which is determined for a given gate voltage and the threshold voltage of the transistor, respectively, are permanently altered by charges which are trapped in the gate double insulating layer. During programming, a positive voltage pulse causes negative charges to be stored at the nitride-oxide interface and inside the nitride, respectively, in the addressed transistors, thereby rendering such transistors permanently blocked. The charges can be disintegrated by a pulse of the reverse polarity or by other erasing processes. One such process, sometimes referred to as "short channel erasure" comprises connecting a positive voltage pulse to the source and drain zone while connecting the substrate and gate to ground potential.
The manufacture of highly integrated circuits (VLSI-very large scale integration-technology) necessitates relatively thin gate oxides (having a maximum thickness of about 50 nm) and relatively flat diffusion zones (smaller than about 0.5.mu.m). These requirements result in a reduction in the avalanche breakdown voltage at the drain-side of the pn-junctions. In instances of short channel erasure of silicon dioxide/silicon nitride double insulating layer memory elements (MNOS transistors), the erasure process (sometimes referred to as a punch-through breakdown) is complicated because the transistors break down before the erasure voltage is reached at the pn-junction of the source-drain zone.
In device components which exhibit a relatively low degree of integration, premature pn-avalanche breakdown of short-channel transistors is avoided, for example, by using thick gate oxide layers (100 to 200 nm) or by producing deep-diffused source/drain zones (1 to 1.5.mu.m). Another means of avoiding premature pn-avalanche breakdown comprises of providing a so-called split gate arrangement which is characterized by a thick gate oxide at the drain edge (see I. R. Cricchi et al., Technical Digest IEDM, Washington, DC, page 126, 1973).
However, when higher degrees of integration are required (VLSI technology), split-gate arrangements can no longer be utilized. Further, additional reductions of the channel length involve serious technological difficulties.